In MPEG video data coding and decoding architectures, various communication schemes have been used so far for permitting the transfer of video data between various processing units. The processing units comprise co-processors implementing functions such as, for example, a variable-length decoding, an inverse quantification, or an inverse discrete cosine transform. For MPEG video data which have a variable size by nature, the data communication architecture that is the most relevant comprises queue memories or FIFO memories (First In First Out), a data bus and a local memory connected to the data bus. The video data are transmitted from a transmitting co-processor to a receiving co-processor via a data bus in the form of packets whose size depends on the granularity of the queues. This transmission of packets of video data is effected by utilizing a push-pop mechanism which consists of popping the video data packet by packet out of the queue memory associated to the transmitting co-processor so as to store them in the local memory, these packets being later pushed in the queue memory of the receiving processor from the local memory. Although such a data architecture permits a certain flexibility of operation, it is particularly costly in terms of bandwidth because of the many data transfers over the data bus for which the communication must be effected via the local memory.